1. Field of the Invention
The present invention relates to integrated circuit design and fabrication. More specifically, the present invention relates to a method and an apparatus to determine a photolithography process model that models the impact of CAR/PEB (Chemically Amplified Resist Post Exposure Bake) on the resist profile.
2. Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be attributed to the dramatic improvements in semiconductor manufacturing technologies which have made it possible to integrate tens of millions of devices onto a single chip.
As semiconductor design enters the deep submicron era, process model accuracy is becoming increasingly important. Inaccuracies in the process model negatively affect the efficacy of downstream applications. For example, inaccuracies in the photolithography process model can reduce the efficacy of optical proximity correction (OPC). Hence, it is desirable to improve process model accuracy.